Integrated circuit including parametric analog elements

ABSTRACT

A design system is provided. In one embodiment the design system includes an input module to receive specification data for a designed circuit including a configurable integrated circuit (IC). The configurable IC includes a number of analog elements for which parameters can be set by the design system, and a plurality of configurable signal path elements including an analog-to-digital converter (ADC) that is utilized in a plurality of different signal paths. The design system further includes a design module to generate a design for the designed circuit based on the specification data, and an output module to set parameters of at least one of the analog elements based on the design. Other embodiments are also provided.

CROSS-REFERENCE TO RELATED APPLICATIONS

This Application is a Continuation of U.S. patent application Ser. No. 14/606,661, filed on Jan. 27, 2015, which is a continuation of U.S. patent application Ser. No. 12/789,991, filed on May 28, 2010, now U.S. Pat. No. 8,966,414, issued on Feb. 24, 2015, which claims the benefit of priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application Ser. No. 61/217,427, filed May 29, 2009, and to U.S. Provisional Patent Application Ser. No. 61/275,593, filed Aug. 31, 2009, all of which are hereby incorporated by reference in their entirety.

TECHNICAL FIELD

The present disclosure relates generally to electrical circuits and more particularly to a framework or environment and method of designing and implementing a circuit using an integrated circuit including parametric analog elements.

BACKGROUND

Conventional methods of designing analog or mixed analog/digital circuits require services of one or more highly skilled analog design engineers. Typically, the design process follows a systematic approach involving a number of distinct steps. These steps include meeting with a customer; creating a preliminary schematic circuit diagram on paper; identifying components that will meet operating specifications of the circuit; simulating the circuit using mathematical or computer programs to verify the design; and building and testing a prototype of the design against the customer specification. Generally, each of the above steps must be repeated one or more times to satisfy customer requirements.

More recently, advanced computerized design tools have been introduced that allow engineers to design an analog circuit using an exemplary or model and to select and to facilitate prototyping of the circuit by interconnecting blocks of sub-circuits on a programmable integrated circuit (IC).

However what all of the existing methods and design the tools share a common deficiency in that they require a high level of expertise in analog and/or mixed signal design in order to be used proficiently.

SUMMARY

An environment and method are provided for designing and implementing a circuit comprising an integrated circuit (IC) including a number of parametric analog elements for which operating parameters can be set. In one embodiment, the method comprises: specifying requirements for the circuit including physical properties to be sensed by the circuit and actions to be taken by the circuit; designing the circuit based on the specified requirements and resources available on the IC; and setting parameters of at least one of the parametric analog circuit elements of the IC based on the circuit design. Generally, implementing the circuit includes designing a number of sensor and/or actuator sub-circuits to be coupled to the IC, and the method further comprises building the circuit including electrically coupling the sub-circuits to the IC.

In a number of embodiments the specifying, designing, and setting parameters, steps are performed using a computer executable code embodied in a computer readable medium on a server coupled to a client computer through an Internet Protocol (IP) network.

BRIEF DESCRIPTION OF THE DRAWINGS

These and various other features of an integrated circuit including parametric analog elements an environment and method for implementing a circuit using the same will be apparent upon reading of the following detailed description with the accompanying drawings and the appended claims provided below, where:

FIG. 1 is a functional block diagram of a circuit including an Integrated Circuit (IC) including parametric analog elements designed and implemented using a framework or environment and method according to an embodiment of the present disclosure;

FIG. 2 is a functional block diagram of a single chip architecture of a parameterizable IC for which operating parameters of analog elements can be set according to an embodiment of the present disclosure;

FIG. 3 block diagram of an embodiment according to the present disclosure of a framework or environment for designing and implementing a circuit including a parameterizable IC, the framework including a server and coupled to a client computer through an Internet Protocol (IP) network;

FIG. 4 is a block diagram illustrating functional modules of a computer design and tradeoff tool according to an embodiment of the present disclosure;

FIGS. 5A and 5B are a top-level flow diagram illustrating a method of designing and implementing a circuit includimg a parameterizable IC using a framework or environment according to an embodiment of the present disclosure;

FIGS. 6A-6G illustrates a series of user interface pages for designing a circuit using a parameterizable integrated circuit (IC) according to an embodiment of the present disclosure;

FIGS. 7A through 7D are a top-level flow diagram illustrating a method of refining and implementing a circuit including a parameterizable IC using a framework or environment according to an embodiment of the present disclosure;

FIG. 8A illustrates a user interface page for a circuit comprising a single sensor-sub-circuit refined using a CTT and method according to an embodiment of the present disclosure;

FIG. 8B illustrates a user interface page for a circuit comprising multiple sensor-sub-circuits refined using a CTT and method according to an embodiment of the present disclosure; and

FIG. 9 illustrates a diagrammatic representation of a machine in the example form of a computer system within which a set of instructions, for causing the machine to perform any one or more of the methodologies, processes, or operations discussed herein, may be executed.

DETAILED DESCRIPTION

A framework or environment and method of designing and implementing an analog or mixed signal circuit comprising one or more parameterizable Integrated Circuits (ICs) is provided. By parameterizable IC, it is meant an IC including configurable and fixed analog sub-circuits, components, or elements for which operating parameters can be set. By mixed signal circuit it is meant a circuit including both analog and digital sub-circuits, components, or elements.

Reference in the description to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the dual protocol input device or method. The appearances of the phrase “one embodiment” in various places in the specification do not necessarily all refer to the same embodiment. The term “to couple” as used herein may include both to directly electrically connect and to indirectly connect through one or more intervening components.

Briefly, the environment and method of the present disclosure enables a user unfamiliar with analog circuit design to design and implement an analog or mixed signal circuit comprising one or more parameterizable ICs based on user specifications of what the circuit is to do, and not what is in the circuit or on the IC. The environment and method according to various embodiments will now be described with reference to FIGS. 1 to 9.

FIG. 1 illustrates a functional block diagram of a host circuit or system 100 comprising or using a circuit 102 including a one or more parameterizable integrated circuits (ICs) 104 according to an embodiment of the present disclosure. In addition, to the circuit 102, the host system 100 can further include a host processor 106 to which a number of drivers and/or controllers 108 are coupled to control or operate any number of external systems, actuators or components 110 including, for example, displays, motors, fans, heating elements etc.

The parameterizable IC 104, described in detail herein below, an include, inter alia, multiple input/outputs (I/O) devices, such as isolation buffers or amplifiers, multiplexers (MUXs), analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). In addition, the parameterizable IC 104, the circuit 102 can further include a sensor interface 112 through which a number of sensors 114 couple to I/O devices of the parameterizable IC, and a number of output devices or actuators 116 coupled to the parameterizable IC through an actuator interface 118. The sensors 114 can include discrete analog sensors adapted to sense one or more of a number of properties or states including pressure, temperature, weight, humidity, air-flow, acceleration, tilt, rotation, position, light, current, voltage, inductive, gas, liquid-level, and touch sensing, such as capacitive sensing, touch screens, touch pads and proximity sensing or any other physical or electrical quantity for which an analog sensing element exists, and for which the parameterizable IC 104 can generate a measurement report or operate an output device or actuators 116. Actuators 116 coupled to the parameterizable IC 104 can include visual or audible indicators, such as a speakers, or LEDs, and/or external systems or controllers therefore. External systems can include, for example, displays, AC motors, DC motors, fans, fuel pumps, instrument gauges, lighting/LEDS, and power control devices, such as battery chargers or power meters, heating elements etc. Additionally, the circuit 102 can further include a human interface device or HID 120 coupled to the parameterizable IC 104 through which a user can interact directly with the parameterizable IC or the host system 100.

FIG. 2 illustrates a functional block diagram of a parameterizable IC 200 according to an embodiment of the present disclosure. Referring to FIG. 2, the parameterizable IC 200 generally includes a number of inputs and output (I/O 202), configurable signal path elements 204, and parameterization sub-circuitry 206, fixed parametric analog circuit elements 208. The I/Os 202 can include a number of devices, such as isolation buffers or interfaces coupled to input output pins of the IC 200, including a number of fixed output pins. By fixed output pins, it is meant output pins electrically coupled either directly to the fixed parametric analog circuit elements 208 or through a signal path that is not configurable or cannot be re-configured after parameterization of the IC. The configurable signal path elements 204 can include multiplexers (MUXs), amplifiers, analog to digital converters (ADCs), and digital to analog converters (DACs). The fixed parametric analog circuit elements 206 generally includes analog blocks, sub-circuits and components such as Analog Comparators, Operational Amplifiers, Programmable Gain Amplifiers, Analog Voltage References, Analog Current References, Voltage Diagnostics, Current Diagnostics, Multiplexers, Analog Switches, Voltage Monitors, Current Drivers, Temperature Sensor, Programmable I/Os, Oscillators, Charge Pump, Voltage Regulators. The parameterization sub-circuitry 206 can include a number of switching elements, fusible links and signal path, through which parameters can be set for the parametric analog circuit elements 206.

In some embodiments, such as that shown in FIG. 2, the parameterizable IC 200 can further include configurable digital circuit elements 210, system resources 212, memory 214, a sampling scheduler 216 to schedule sampling of the ADCs, and a specialized or dedicated interface, such as a host IF 218, through which the IC is coupled to a host system or processor (not shown in this figure). The configurable digital circuit elements 210, can include first-, second-, or third-order gain and offset compensation for temperature, and non-linearity compensation; digital signal de-bouncing; filtering options such as the coefficients and lengths of filters; FIFO buffer length; Interrupts and flagged events such as FIFO is full or sampled level is above a warning level; Communication protocol, hich protocol is the downstream processor expecting that is selected from a short list with the default protocol being, for example, I2C protocol. System resources 212 can include clocks, counters, etc.

Memory 214 can include any number of suitable volatile and/or non-volatile semiconductor memory devices, such as registers, used to temporarily or permanently store data or instructions for setting parameters, configuring, controlling, and accessing the parametric analog circuit elements 208 or digital circuit elements 210.

In one embodiment, the memory 214 includes multiple registers to hold alternate parmuneterrzatiorm or configuration settings to support switching between different power consumption or operating modes. The paratneterizable IC 200 can switch between these alternate configuration settings based on a timer, a sensed condition, and/or a mode change command received from the host system. The alternate parameterization or configuration settings are calculated during circuit design, as explained in detail below, by a circuit design tool (CDT), or by a circuit trade-off tool (CTT). Generally, initial parameterization or configuration settings are calculated during circuit design or optimization. However, optionally the parameterization settings can be calculated or updated in real-time, for example, through a host system.

An embodiment of a framework or environment 300 for designing and implementing a circuit including a parameterizable IC using a circuit design tool (CDT) and a circuit trade-off tool (CTT) will now he described with reference to FIGS. 3 and 4.

Referring to FIG. 3, the environment 300 generally comprises computer executable code or instructions (CDT and CTT software 302) embodied in a computer readable medium and running in an operating system on a server computer 304. A client computer 306 is coupled to the server computer 304 through an Internet Protocol (IP) network 308, such as wide area network, or the Internet or World Wide Web. The environment 300 further comprises a system database 310 coupled to the server computer 304, and storing data on available sensors, actuators, and parameterizable ICs. Data stored can include information on accuracy, range, cost, availability, power requirements, physical size, and/or heat dissipation required. The system database 310 can be directly coupled to the server computer 304, as shown, or can be remotely located from the server computer and coupled thereto through the IP network 308. In the latter embodiment, the system database 310 can be a distributed or virtual database, including, for example, information on sensor on accuracy, range, and cost made available and kept up to date by the sensor manufacturer over the Internet.

Additionally, as in the embodiment shown, the environment 300 can further include a client database 312 coupled to the client computer 306, for storing locally a subset of the data stored in the system database 310, completed analog circuit solutions, and/or work-in-progress. For example, the client database 312 can store configuration data on a completed analog circuit solution to enable a user to quickly configure and calibrate additional implementations of the completed analog circuit substantially without repeating all of the design, simulation, and testing steps of the original analog circuit solution, and without reconnecting or re-synchronizing with the system database.

In another aspect of the invention, the software 302 further comprises instructions that enable the user interact live, with an analog expert about a circuit design or solution that may be starting, in progress, or substantially complete. By analog expert, it is meant one who is knowledgeable in one or more of analog circuit specification, design, simulations, calibrations, prototypes, implementations, and layouts. Preferably, the software 302 further comprises instructions that enable the user to interact with the analog expert verbally or through text messages, including email and instant messaging, via the internet or other IP network 308 or verbally over a telephone network. More preferably, the analog expert has access to and the ability to override specified requirements, including measurement requirements, output requirements, and overall circuit requirements, and to override automatically calculated solutions of the original analog circuit solution via the IP network 308. The analog expert can access the environment through a separate computer 314 directly coupled to the IP network 308, as shown, or can access the IP network through the server computer 304.

A block diagram illustrating functional modules of CDT and CTT software 400 according to an embodiment of the present disclosure is shown in FIG. 4. Briefly, the software 400 includes: a input module 402 for reading or receiving default settings and user specified requirements including measurement requirements, output requirements, overall circuit requirements, and, optionally, overrides of the default settings; a design module 404 to: (i) design based on the specified requirements a circuit comprising an integrated circuit (IC) including a number of parametric analog circuit elements for which operating parameters can be set and a number of sub-circuits electrically coupled thereto; and (ii) verify the circuit design satisfies a number of the specified requirements; and an output module 406 to: (i) set parameters of at least one of the parametric analog circuit elements of the IC based on the circuit design; and (ii) communicate to the user instructions for electrically coupling the number of sub-circuits to the parameterizable IC to implement the circuit.

The design module 404 includes a sub-circuit evaluation module 408 for reading or receiving manufacturer-specified characteristics of the sub-circuit components and evaluating a candidate sub-circuit; a sensor and actuator evaluation module 410 for reading or receiving manufacturer-specified characteristics of candidate sensors and/or actuators of the sub-circuit including cost, power consumption, and/or availability etcetera and evaluating a candidate sensor; an IC evaluation module 412 for evaluating a candidate parameterizable IC; an ADC utilization module 414 for calculating the ADC usage of the sensor, sub-circuit and/or the complete circuit; a sensor accuracy module 416 for calculating the, effective sensor reading accuracy without the contribution from the ADC; an aggregate accuracy module 418 for calculating the aggregate accuracy of the sensor with multiple readings to the ADC per report period; and a power consumption module 420 for calculating power consumption of a sub-circuit and/or the complete circuit.

Note the circuit or sub-circuit alternatives, e.g. circuits or sub-circuits using alternative sensors or other components or other sub-circuit configurations, can be generated by a separate design tool CDT or circuit tradeoff tool CTT. When the initial alternative circuits are generated by the CDT, these alternatives are inputs to the CTT. When the alternative circuits are generated or expanded by the CTT, the CTT uses a primary example circuit or sub-circuit and a set of rules for identifying candidate alternative components or sub-circuit configurations. An example of an alternative sub-circuit configuration follows rules to take a sensor that is connected to the IC using differential inputs and modify the connection to use a single-ended input with some additional biasing. In this example, the single-ended connected sensor has less accuracy than the same sensor connected differential. However, the single-ended connection uses one less IC pin and may have enough accuracy to meet the user specifications and because one less pin is used, can enable use of a less expensive IC for the complete circuit.

The functions performed by each of the above modules, as well as sub-modules not shown in this figure, will be described in greater detail below with reference to methods of designing and refining performance of a circuit including a parameterizable IC according to embodiments of the present disclosure.

Embodiments of methods of designing, simulating, implementing, and testing a mixed signal circuit comprising a parameterizable IC will now be described with reference to the flowchart of FIGS. 5A and 5B and exemplary user interface pages of FIGS. 6A-6G.

Referring to FIG. 5A and FIG. 6A, in a first block or step, the user begins by specifying the requirements of the circuit. Generally, the specifying step can include specifying parameters such as temperature, flow, level, pressure, shock, tilt etc., to be monitored or measured, as well as an expected range and desired accuracy for each. Optionally, the step may further include querying and allowing the user to specify additional system level requirements including power, diagnostics, alerts, and cost goals or limitations, and/or a vendor or manufacturer for sensors to be used with the circuit. In certain embodiments, the system will automatically provide default values for requirements not specified by the user. For example, where the user has not specified a range or accuracy for a temperature to be measured, the system can automatically provide a default range of 0 to 100° C. and an accuracy of ±2.5%. Alternatively, the user may specify a bias or general preference in default values, for example, by selecting between ‘more accurate’ or ‘higher performance’ and ‘lower cost’.

Sub-steps of an exemplary specifying step are described below with reference to the flow chart of FIG. 5A. Once the basic system level and measurement specifications are input, some of the following steps are optional since some of the additional information is optional and default values can be automatically provided. Referring to FIG. 5, the specifying step begins with the user entering a circuit specification (step 500). Circuit specifications can include, for example, sharing power voltage levels at known voltages and limited variations. Next, the user selects circuit goals including cost and power (step 502), and selects a measurement type (step 504). As noted above, measurement types can include temperature, flow, level, pressure, shock, tilt, or vibration or any other physical quantity for which an analog sensing element exists. The user then enters measurement specifications including accuracy requirements (step 506). The system automatically queries the sensor database and shows sensors meeting specifications (step 508). If the user does not select one of the sensors meeting specifications, or requests alternatives, the system again queries the sensor database and shows alternative sensors (step 510). The user then queries the system to estimate cost and power versus circuit goals (step 512). The user then queries the system to create an ordered list of candidate sensors (step 514). The user then selects a sensor for current measurement (step 516). If needed, the system or user pairs the sensor with a temperature sensor (step 518). The system then prompts the user to add or edit sensor (step 520). If a sensor is to be added or edited, the system returns to step 504 and prompts the user to selects a measurement type. If no sensor is to be added or edited, the system then prompts the user to add or edit circuit specifications (step 522). If a circuit specification is to be added or edited, the system returns to step 500 and prompts the user to enter a circuit specification. If no circuit specification is to be added or edited, the specifying step is complete.

As part of the specification step, the system accesses a sensor database and identifies a subset of suitable sensors for the parameters to be measured, which may then be displayed for the user in a ‘performance summary’ identifying available sensors along with predetermined pertinent information about each, such as cost, accuracy, range and/or availability. It will be understood that this enables the user to select or specify a particular model of sensor from the list of suitable sensor. If the user fails to specify a sensor, the system can automatically choose one satisfying the default range or accuracy using predetermined criteria base on factors such as cost, rating, or reliability.

Referring to FIG. 5B and to FIG. 6B, the system automatically calculates or models the circuit using a parameterizable IC and the sensors selected in the proceeding step, and prepares to simulate operation of the modeled circuit (step 524). As part of this step, the system displays design performance data, such as accuracy over temperature, accuracy over range, and/or power consumption. The system also displays a complete parts list of circuit components, including external sensing components. Optionally, the system prepares and displays to the user a simplified schematic, block diagram or wiring diagram of the complete circuit. Now, the user may accept or reject the modeled circuit, for example by returning to the specifying step and further specifying circuit requirements. Alternatively, the system may allow the user to override system generated choices, for example, selecting a different sensor or by overriding any of the choices listed in FIG. 6B. As shown, in some embodiments the system warns the user if any overrides or changes do not meet the requirements specified in step.

Next, the system simulates operation of the approved or accepted modeled circuit (step 526). Referring to FIG. 6C, the user can select a measurement type, a sensor or sensors for the simulation and a simulation time extent. The system then generates signals and/or noise for the selected sensors. The simulated input signals can be auto-generated in background or be pre-calculated prior to beginning the simulation. Referring to FIG. 6D, the system run the generated signal and noise through the analog conditioning and signal processing and output selections. The system then generate a simulated output (including intermediate outputs and feedback signals if any) and shows both input and output simulation signals in a variety of formats including graphically over time, and available in comma separated value file format. Preferably, the user interface page enables the user to annotate input and output data with notes, label interrupt events and output or export the simulation results as a saved or printed document or data file. Optionally, the system provides the user with the choice of running the simulation faster with limited data, or more robust, slower simulation.

Referring to FIG. 6E, the system provides the user with the ability compare results of multiple simulations. In certain embodiments, the system simplifies the comparing of multiple simulations with different design details or different input sensor signal and noise to enable the user to evaluate the circuit performance for specific sets of sensor outputs. The system can also enable the user to modify earlier design decisions based on what is learned during simulation. Specifically, the system can then determine whether the results of the simulation are satisfactory and the modeled circuit meets the specified requirements (step 528). If not, the user may repeat the simulation with different selections or return to the specifying step and further specify or edit circuit requirements.

If the results of the simulation of the modeled circuit are satisfactory, acircuit is built using a parameterizable IC (step 530). Generally, this is accomplished by the user placing the parameterizable IC in an evaluation board or test fixture, coupling the board or fixture to the client computer, for example through a USB connection, and downloading parameterization data to the IC. The system then tests the circuit (parameterized IC) using simulated sensor signals and noise (step 532). The system verifies whether the results of the test are satisfactory and the circuit meets the specified requirements (step 534). If not, the user may return to the specifying step and further specify or edit circuit requirements. If the results of tests of the modeled circuit are satisfactory, the user completes construction of the circuit by coupling the parameterizable IC to the selected sensors, inputs, outputs and the host system through the evaluation board. The system can also suggest board layout service companies and/or calibration service companies and/or preferred components and/or preferred distributors and/or alternate suppliers, and/or worst-case component lead-time. The user can alternatively use the evaluation board to send simulation outputs to the host processor for testing of the host processor hardware (interface) and/or software.

At this juncture, the design, simulation and testing of the mixed signal circuit is complete and the user may choose to end the process. Alternatively, the user may elect to calibrate the completed and tested circuit in an optional calibration step (step 536). Referring to FIG. 6F, the user performs calibration measurements offline, and then enters calibration measurement data to the system through the client computer. The system then transforms the calibration measurements into calibration settings, e.g. offset, gain, and non-linearity correction data for the corresponding nonvolatile memory in the parameterized IC. The system also checks that the calibration settings are within allowable ranges for components of the parameterized IC and that calibrated, parameterized IC meets all specified requirements of the circuit (step 538). If the calibration check is satisfactory, the calibration data is formatted for easy transfer to the IC through a USB connection and the evaluation board, and the process is ended. If not, the use may choose to repeat the calibration process (step 536) or to return to the specifying step and further specify or edit circuit requirements.

Referring to FIG. 6G, in another aspect of the invention the user may optionally at in point in the process select or click on a live design support tab in the user interface window to interact with an analog design expert verbally or through text messages via the world wide web or other Internet Protocol network. In addition to be able to answer questions, the integrated design tool and live support allows the design expert to access details of the users design remotely, and thereby review and if necessary correct the specification, design, simulation, prototype, testing and calibration of the circuit. As a result, an inexperienced user can have confidence in his or her circuit design and implementation.

Prior to describing a method of refining performance of a circuit using the CDT and CTT software it is instructive to provide general outlines of an approach to aggregating a set of accuracies, of an approach to estimating the number of consecutive raw samples to compensate for the loss of inaccuracy at the ADC, and of an approach to determining ADC utilization.

Aggregating a Set of Accuracies

Aggregating a set of accuracies enables a set of accuracy values to be combined into a single ‘aggregated’ accuracy value. The following description develops a general approach to aggregating a set of accuracies, e.g. {ai}, is shown in Equation 1. This general form of the aggregate sum is equivalent to a simple sum when m is equal to one. This aggregate sum is equivalent to the Root-Sum-Squared (RSS) when m is equal to two.

$\begin{matrix} {{{Aggregate\_ Sum}\mspace{11mu} \left( {\left\{ a_{i} \right\},m} \right)} = \left( {\sum\limits_{i}\; \left( a_{i} \right)^{m}} \right)^{({1/m})}} & (1) \end{matrix}$

where m≧1 and usually m=1 or m=2. Equation 1 can also be used to combine two or more aggregate sums. When aggregate sums are combined, it is not necessary for the in values to be the same. For example, an aggregate sum can be calculated with an m value of say two. In addition, a second disjoint aggregate sum can be calculated with an m value of say 1.8, and, these two aggregate sums can be combined using Equation 1 with say an m value of one.

The calculation of the aggregate accuracy for an ideal ADC is shown in Equation 2.

Aggregate_Accuracy(Ideal_ADC)=Agregated_Sum({a _(i) },m)   (2)

where ADC_Accuracy∉{a_(i)}. This is simply the aggregated accuracy without any contribution from the analog-to-digital conversion.

Estimating a Number of Raw Sensor Readings

The estimate of the number of consecutive raw sensor readings N combined with a box-car-like filter that effectively averages the readings and decreases the effective noise at the ADC by the square root of the number of readings is shown in Equation 3.

$\begin{matrix} {N = \left( \left\lbrack \frac{({ADC\_ Accuracy})^{2}}{\begin{matrix} {\left( {{Re}\mspace{11mu} {port\_ Accuracy}} \right)^{2} -} \\ \left( {{Aggregate\_ Accuracy}({Ideal\_ ADC})} \right)^{2} \end{matrix}} \right\rbrack \right)^{p}} & (3) \end{matrix}$

where usually p=1. N is the estimate of the number of consecutive raw samples to filter together to compensate for the loss of inaccuracy at the ADC.

In addition, p is usually one or greater than one and very near to one. Another alternative to estimating N is to use a power other than two in Equation 3.

A different but related calculation of the number of samples taken between measurement reports to the host follows from the optional specification of the minimum sample rate (Nu) is shown in Equation 4. The user can specify the minimum sample rate to bound a latency of the sensor measurement alarm to the host. An example of a sensor measurement alarm is a measurement value that is greater than an alarm threshold. The sensor measurements checked for a potential alarm can be one raw measurement, several raw measurements, or several raw measurements combined using a filter.

$\begin{matrix} {N_{u} = \left\lceil \frac{{Minimum\_ Sample}{\_ Rate}}{Report\_ Rate} \right\rceil} & (4) \end{matrix}$

ADC Utilization

To enable the separation of a circuit with multiple sensors into independent sensor-sub-circuits, it is helpful if maximum power consumption and/or maximum ADC utilization percentage is specified or assumed for each sensor-sub-circuit. These specs are optional.

An alternative is to account for the other sensors and calculate the resulting sums for power consumption and ADC utilization percentage. These totals are then compared to specified or assumed limits. A total power consumption limit is optional. Of course, the total of the ADC utilization percentages cannot be greater than 100% since the ADC cannot be used more than 100% of the time. In addition, there may be an optional system requirement for remaining spare capacity of the ADC. For example, if there was such a requirement and its value was say 20%, then the total of the ADC utilization percentages cannot be greater than 80%.

An embodiment of a method for refining a circuit comprising a parameterizable IC using the CDT and CTT software will now be described with reference to the top-level flow diagram of FIGS. 7A through 7D. Referring to FIG. 7A, the method begins with reading or receiving user inputs or default settings from a CDT (702). Generally, these inputs or settings include one or more overall candidate circuits, each comprising one or more sub-circuits. For each sub-circuit, these inputs or settings can include sensor report accuracy, sensor report rate, optional power consumption limit, optional ADC capacity percentage limit, sensor operational temperature minimum and maximum, contributions to the degradation of nominal sensor reading accuracy including drift since calibration, digital and analog voltage source tolerances, user-specified operational temperature range, calibration state, and sensor-sub-circuit tolerances. For the overall candidate circuits, these inputs or settings can include one or more candidate parameterizable ICs and its associated ADC characteristics.

Optionally, inputs from the CDT can further include a listing of all major circuit elements of a candidate circuit design, referred to hereinafter as the Major Circuit Elements List (MCEL). The MCEL can include or list one or more sensors, actuators, a number of parameterizable ICs, reference or supply voltages and any of number of discrete, external components needed to couple the candidate-circuit design to sensors and/or actuators and to the host processor or host communication channel. Generally, these circuit elements and components are allocated to one of the following categories: (i) the set of sensors; (ii) the set of actuators; (iii) parameterizable IC; (iv) the set of remaining circuit components suchas resistors and voltage references; and (v) the set of digital and analog voltages. Alternatively or additionally, as noted above inputs from the CDT can further include circuit or sub-circuit alternatives, e.g. circuits or sub-circuits using alternative sensors, other components, or other sub-circuit configurations. Alternatively, the CTT can expand the sub-circuit alternatives provided by the CDT.

Next, user inputs are read or received from CTT (704). These input can be entered, for example, through a user input module and can include or specify target characteristics for the overall circuit, any of the sub-circuits or sensors. Optionally, the user inputs can override inputs from the CDT.

An assessment or evaluation is made of a first of a number of candidate sub-circuits (706), by evaluating each candidate sensor for the current sub-circuit candidate (708). Evaluation of a candidate sensor begins with reading or receiving manufacturer-specified characteristics of the current candidate sensor (710). These characteristics of the candidate sensor can include power consumption, a nominal sensor reading accuracy, and the maximum sensor-reading rate at a user-specified operational temperature range. The characteristics can be received directly from a manufacturer-supplied database coupled directly to the CTT, coupled to the CTT through an IP network, or through the CDT. The candidate sensor is evaluated to ascertain whether it meets predetermined specified criteria for the sub-circuit (712). Specified criteria can include, for example, cost, temperature range, power consumption, and/or availability. This initial power consumption check is based on a maximum user specified report rate and an optional minimum sensor sample rate, and on other sub-circuit elements allocated to the sensor-sub-circuit.

If the sensor does not meet any of the specified criteria, it is discarded, and the next candidate sensor for the current sub-circuit is evaluated (714).

If the sensor does meet all or substantially all of the specified criteria, an effective sensor reading accuracy is calculated for without degradation of accuracy from the ADC (716), referred to hereinafter as Aggregate_Accuracy(Ideal ADC). Referring to equations 1 and 2 above, when, for example, A is two, calculate the square root of the sum of the squares of:

-   -   a) accuracy component of the raw sensor reading at its nominal         temperature;     -   b) accuracy tolerance component of drift since calibration;     -   c) accuracy tolerance of the digital and analog voltage sources;     -   d) accuracy degradation due to the user-specified operational         temperature range; and     -   e) accuracy tolerance of the other sensor-sub-circuit elements

Results of the above calculations are compared to a user specified accuracy of sensor reports to the host (718). As a value larger than a user specified accuracy of sensor reports to the host represents a less accurate result, if the result of the above calculation is greater thanthe user specified, the candidate sensor is discarded and the nest candidate sensor for the current sub-circuit is evaluated (720).

If the result of the above calculations is less than the user specified, an assessment or evaluation is made of a first of a number of candidate configurable ICs (722). Evaluation of a candidate IC begins with calculating an aggregate accuracy of the total effective sensor reading accuracy, including the contribution from reading of the ADC associated with the current candidate IC (724). Referring to FIG. 7B, the result of this calculation is compared to the user specified accuracy of sensor reports to the host (726). If the result of the calculation is less than or equal to the user specified accuracy of sensor reports to the host, i.e. a more accurate result, then the candidate sensor can be used without combining multiple raw sensor readings (e.g., N=1) (728). Otherwise., the number of consecutive raw sensor readings N combined with a box-car-like filter is calculated that averages the readings and decreases the effective noise at the ADC by the square root number of readings combined (730). (See Equation 3 above) For example, if the goal or target sensor report accuracy is 14 bits or 2⁻¹⁴ or about 0.000061; the square root (RSS) of the accuracy contributions assuming an ideal ADC is 15.6 bits or 2^(−15.6) or about 0.000020; and, the ADC accuracy is 12 bits or 2⁻¹² or about 0.000244, then the resulting number of samples is estimated as: N=Ceiling(((0.000244)²)/((0.000061)²−(0.000020)²)) or about 18, assuming quantization noise does not prevent the gain realized from combining multiple samples. Note, that raising the resultant N to some power slightly larger than one can increase this estimate of the number of samples to account for a less ideal noise environment.

Next, a check is performed to determine if the user specified a minimumsample rate (732). If the user specified a minimum sample rate, then the number of samples for the user specified rate (Nu) is calculated, and N is replaced with the maximum of N or Nu (734). (See Equation 4 above) The user can specify the maximum sample rate, for example, to bound or limit a latency of the sensor report to the host. If the user has not specified a minimum sample rate, then the raw sensor-reading rate is calculated as a product of a user specified sensor report rate and the number of consecutive raw samples N (736). The resulting product is compared to a maximum raw sensor-reading rate specified by the sensor manufacturer (738). If the calculated rate is greater than the maximum raw sensor-reading rate, the current combinationof sensor and IC are discarded and the next candidate combination for the sensor-sub-circuit is evaluated (740).

If the calculated rate is less than the maximum raw sensor-reading rate, the ADC utilization of the current IC is calculated based on the raw sensor-reading rate (742). Referring to FIG. 7C, the calculated ADC utilization is compared to an optionally specified ADC utilization (744). If the calculated ADC utilization is beyond the specified ADC utilization, the current ombination of sensor and IC is discarded and the next candidate combination for the sensor-sub-circuit is evaluated (746).

If the calculated ADC utilization is less than the specified ADC utilization, power consumption of the sensor and/or sensor-sub-circuit is calculated based on the raw sensor-reading rate (748). The calculated power consumption is compared to an optionally specified power consumption (750). If the calculated power consumption is beyond that specified, the current combination of sensor and IC is discarded and the next candidate combination for the sensor-sub-circuit is evaluated (752).

If the power consumption is less than the specified power consumption, the current combination of sensor and IC is saved or recorded for later presentation to the user (754), and a check performed to determine if the current IC is the last candidate IC for the sensor-sub-circuit (756). If the current IC is not the last candidate IC, the current candidate IC is indexed (758) and the next candidate IC for the sensor-sub-circuit is evaluated.

Next, a check is performed to determine if the current sensor is the last candidate sensor for the sub-circuit (760). If the current sensor is not the last candidate sensor, the current candidate sensor is indexed (762) and the next candidate sensor for the sub-circuit is evaluated.

A check is performed to determine if the current sub-circuit is the last sub-circuit for the overall circuit (764). If the current sub-circuit is not the last sub-circuit, the current sub-circuit is indexed (766) and the next sub-circuit is evaluated.

Referring to FIG. 7D, after all sub-circuits have been evaluated, a check is performed to determine if system or overall circuit level results have been requested (768). If system or overall circuit level results have not been requested, an output module shows the sub-circuit combinations that have not been discarded (770).

If system level results are requested, the method continues with evaluation of the overall circuit, including combinations of each sub-circuit with the same associated IC (772). It is noted that there may be many such possible combinations of sub-circuits, sensors and the associated ICs. In one alternative embodiment, the method may further include a step in which the CTT automatically selects only the combinations with the more desirable characteristics so the user gets an answer more quickly (and with fewer alternate combinations that are likely less desirable). The ADC utilization of the overall circuit, including combination of all sub-circuits and the associated IC is calculated based on the raw sensor-reading rate of each sensor (774). The calculated ADC utilization is compared to an optionally specified ADC utilization (776). If the ADC utilization is beyond the optional specified amount or is greater than 100%, the current combination of sensors, sub-circuits, and IC is discarded (778).

If the calculated ADC utilization is not beyond the specified ADC utilization and/or is less than 100%, the power consumption of the overall circuit, including combination of all sub-circuits and the associated IC is calculated based on the raw sensor-reading rate of each sensor (780). The calculated power consumption is compared to an optionally specified power consumption (782). If the power consumption is beyond the optional specified amount or is greater than 100%, the current combination of sensors, sub-circuits, and IC is discarded (784).

If the power consumption is less than the specified power consumption, a check is performed to determine if the current combination of sub-circuits is the last combination (786). If the current combination is not the last combination, the current combination is indexed (788) and the next combination is evaluated. After all combinations of sub-circuits have been evaluated, the output module shows the user all circuit and sub-circuit combinations that have not been discarded (770).

It will be understood the above-described method is simplified for clarity and the method can include any number of additional steps or sub-steps without departing from the spirit and scope of the present invention. For example, the method can further include reporting candidate-circuits not meeting target values but within a specified amount or percentage of the target values with the results annotated accordingly. Additionally or alternatively, the method can further include steps for altering modes of operation of the candidate circuit or scheduling sampling of an analog-to-digital conversion to meet target values.

Exemplary, user interface pages for a circuit refined using tools and method according to an embodiment of the present disclosure will now be described with reference to FIGS. 8A and 8B. In particular, FIG. 8A illustrates a user interface page for a one sensor-sub-circuit refined using a CTT and method according to an embodiment of the present disclosure, and FIG. 8B illustrates a user interface page for a circuit comprising multiple sensor-sub-circuits refined using a CTT and method according to an embodiment of the present disclosure.

Referring to FIG. 8A, it is seen that the user interface (UI) page includes a number of sensor characteristics for a number of candidate sensors including accuracy, rate, power, sense range, temperature, cost, availability, calibrations, digital and analog voltages, manufacturers and distributors. The UI page further includes a number of slider widgets to enable the user to scroll through all candidate sensors, and nudge the user specified measurement accuracy and nudge the user specified measurement report rate. These adjustments to measurement accuracy and report rate enable the user to consider alternative measurement specifications without going all the way back to the CDT. In addition, the UI page can include a number of fields to enable the user to input target values such as minimum and maximum temperature goals and/or check boxes to the right side of the figure to include or exclude the power and cost related to the sensor-sub-circuit beyond the sensor itself. For example, the check box can instruct the CTT to consider the sensor only instead of the entire sensor-sub-circuit for characteristics like cost and power consumption. Optionally, the fields of the candidate sensors can be ordered, shaded, or colored to indicate a priority or preference in candidates based on a previously entered weighted list of target-circuit characteristics. These priorities and/or preferences are used to calculate the columns (of sensors) in the table so that the candidate sensors for the current sub-circuit are ordered from most desirable to least desirable from say left to right.

FIG. 8B includes many of the same fields as FIG. 8A, with the difference that the columns are for the current selected or preferred sensor-sub-circuits that form the complete circuit rather than the candidates for one sub-circuit. In addition, FIG. 8B preferably further includes fields providing information on the total system or overall circuit design such as total power and cost.

Primary trade-offs and/or optimized characteristics for the circuit likely to be important to the user include: sensors and actuators selected for circuit; accuracy of results reported from each sensor to the host; power consumption for the circuit and also attributable to each sensor; rate of sensor reports from each sensor to the host; operational temperature range; cost for the circuit and also attributable to each sensor; heat dissipation; failure rate; common failure types; and mass. In addition, there are secondary characteristics for the circuit, the sensor-sub-circuit, or the individual circuit elements that may be important or of interest to the user. These include: availability of each circuit element on the MCEL; list of calibration measurement opportunities for each sensor and/or actuator and its sub-circuit; list of digital and analog voltage sources attributable to each sensor; list of manufacturers and distributors for each element; maximum or typical latency for sensor reports to the host; storage temperature range; and the storage and/or operating environmental conditions and/or requirements. The above list is referred to hereinafter as the Trade-offs and Optimized Characteristics List TOCL.

Tradeoffs to Reduce Power Consumption

Opportunities or steps to reduce power consumption, and resultant heat generation for the completed circuit, using the circuit tradeoff tool generally include: operating sensor or signal acquisition chains or paths at or near a minimum supply voltage; use lower bias currents in programmable gain amplifiers (PGAs) and analog-to-digital converters (ADCs); disable PGAs and couple input signals from sensors directly to the ADC; operate the ADC at a high, efficient sample rate and maximize the power down time of the PGAs and ADCs between samples; and switch off at least some signal paths in the circuit between a top-level operating mode and an idle or standby mode.

Several of the above opportunities or steps will now be described in more detail. It will be understood that the first and simplest step to reduce power consumption is to operate sensor or signal acquisition paths at or near a minimum supply voltage for which the sensor can reliably and accurately operate, Information on the minimum supply voltage can be obtained from manufacturer databases and accessed through the CDT. Similarly, it will be further understood power consumption can be further reduced by lowering bias currents in PGAs and ADCs. If desired, greater offset and gain adjustment can be used after the analog signal is sampled to compensate for the lower bias current.

Finally, as noted above, the parameterizable IC can include multiple registers to hold alternate configuration settings calculated by the CDT or CTT during circuit design or optimization to support switching all or part of the circuit between different operating modes. When the circuit is not in an active operating mode, power to some or substantially the entire major the circuit elements can be turned off or reduced to place the circuit in a lower power consuming stand-by mode. The opportunity to turn off or use a stand-by mode for each of the circuit elements depends on the set of circuit elements selected and the duty cycle of their use. For particularly power-conscious solutions, there may be more than one operating mode and/or one stand-by mode available depending on the sensor-reading rates, the available calibration measurements, and the operating temperature range. For example, circuit elements in a sensor path monitoring a critical temperature may be operated either in a normal, full operating mode or in one of several reduced power operating modes, each with successively lower sampling frequency. At the same time another sensor path monitoring a less critical parameter, such as a half-full tank level, may be switched between a single operating mode and a standby mode.

The circuit or signal path can switch between these alternate operation modes based on a timer, a sensed condition, and/or a mode change command received from the host system. Even so, it is likely that the operating modes are selected so that all of the enabled sensor measurements are reported to the host at the same rate.

The sensor raw reading rates can be different from the sensor report rates to the host since multiple sensor readings can be processed before reporting the effective measurement to the host. In addition, some of the sensor report rates can be zero depending on the needs of the top-level operating mode. This top-level operating mode can be simplified to the level of an individual sensor by ignoring the other sensors and their sub-circuits except for the allocation by the CDT of the non-sensor circuit elements to the sensor of interest. Accounting for this allocation enables calculations of power consumption or cost attributable to each of the user-specified sensor measurements.

FIG. 9 shows a diagrammatic representation of a machine in the form of a computer system 900 within which a set of instructions, for causing the machine to perform any one or more of the methodologies, processes, or operations discussed herein, may be executed. In some embodiments, a computer system 900 may be used for sensing movement of an actuator across a surface of a window in an enclosure of an interface device.

The computer can operate as a standalone device or, in alternative embodiments, may be connected (e.g., networked) to other computers. In a networked deployment, the computer may operate in the capacity of a server or a client computer in server-client network environment, or as a peer computer in a peer-to-peer (or distributed) network environment. The computer may be a server computer, a client computer, a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a network router, switch or bridge, or any computer capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that computer. Further, while only a single computer is illustrated, the term “computer” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The example computer system 900 includes a processor 902 (e.g., a central processing unit (CPU) a graphics processing unit (GPU) or both), a main memory 904 and a static memory 906, which communicate with each other via a bus 908. The computer system 900 may further include a video display unit 910 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)). The computer system 900 also includes an alphanumeric input device 912 (e.g., a keyboard), a cursor control device 914 (e.g., an interface device), a disk drive unit 916, a signal generation device 918 (e.g., a speaker) and a network interface device 920.

The disk drive unit 916 includes a machine or computer-readable medium 922 on which is stored one or more sets of instructions (e.g., software 924) embodying any one or more of the methodologies or functions described herein. The software 924 may also reside, completely or at least partially, within the main memory 904 and/or within the processor 902 during execution thereof by the computer system 900, the main memory 904 and the processor 902 also constituting computer-readable media.

The software 924 may further be transmitted or received over a network 926 via the network interface device 920.

While the computer-readable medium 922 is shown in an example embodiment to be a single medium, the term “computer-readable medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term “computer-readable medium” shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present invention. The term “computer-readable medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical and magnetic media, and carrier wave signals.

Thus, embodiments of circuit trade-off tools and methods for using the same to optimize a circuit including a parameterizable IC have been described. Although the present disclosure has been described with reference to specific example embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the invention. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

The Abstract of the Disclosure has been provided to comply with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It may be submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure may be not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

In the forgoing description., for purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the control system and method of the present disclosure. It will be evident however to one skilled in the art that the present interface device and method may be practiced without these specific details. In other instances, well-known structures, and techniques are not shown in detail or are shown in block diagram form in order to avoid unnecessarily obscuring an understanding of this description. 

What is claimed is: 1-22. (canceled)
 21. A integrated circuit development environment comprising: an input module for receiving specification data for a configurable circuit comprising at least one analog element and a plurality of configurable signal paths; a design module for generating a first design based on the specification data; and an output module for setting parameters of the at least one analog element and for setting parameters for at least one of the plurality of configurable signal paths, the setting parameters based on the first design.
 22. The integrated circuit development environment of claim 21, wherein the at least one analog element comprises an analog-to-digital converter (ADC).
 23. The integrated circuit development environment of claim 22, wherein the design module comprises an ADC utilization module, the ADC utilization module for setting ADC utilization by defining parameters for the plurality of configurable signal paths.
 24. The integrated circuit development environment of claim 21, wherein the specification data comprises: properties to be detected by the configurable circuit, once configured; and actions to be executed by the configurable circuit, once configured.
 25. The integrated circuit development environment of claim 21, further comprising a communication module for receiving outputs from the configurable circuit, once configured.
 26. The integrated circuit development environment of claim 25, wherein the design module generates a second design based on the specification data and the output from the configurable circuit.
 27. The integrated circuit development environment of claim 21, wherein the output module provides program code to specify at least one sub-circuit coupled to the configurable circuit.
 28. The integrated circuit development environment of claim 25, wherein the at least one sub-circuit comprises a sensor sub-circuit or an actuator sub-circuit.
 29. The integrated circuit development environment of claim 21 further comprising a calibration module for calibration of the configurable circuit.
 30. An integrated circuit comprising: at least one configurable analog element; a plurality of configurable signal paths coupled to the at least one configurable analog element; a configuration circuit coupled to the at least one configurable analog element and the plurality of configurable signal paths, the configuration circuit for receiving parameters settings, the parameter settings derived from specification data of the integrated circuit.
 31. The integrated circuit of claim 30, wherein the at least one configurable element comprises an analog-to-digital converter (ADC).
 32. The integrated circuit of claim 31, wherein the ADC is configured, in part, based on a configuration of at least one of the plurality of configurable signal paths.
 33. The integrated circuit of claim 30, further comprising a communication circuit for transmitting data to a development environment based on the parameters of the integrated circuit and at least one action executed by the integrated circuit.
 34. The integrated circuit of claim 33, wherein the communication circuit is for receiving configuration information from the development environment, the configuration information for the configuration circuit.
 35. The integrated circuit of claim 33, wherein the communication circuit is for receiving calibration information from the development environment transmitted data to the development environment.
 36. The integrated circuit of claim 30 further comprising at least one sub-circuit coupled to the at least one configurable analog element.
 37. A method comprising: receiving a plurality of parameters for at least one configurable analog element and at least one signal path, the plurality of parameters based on a design corresponding to specification data for a configurable circuit, the specification data defining properties and actions of the configurable circuit; configuring the at least one configurable analog element and the at least one signal path based on the received plurality of parameters; transmitting an output based on execution of a plurality of instructions by the at least one configurable analog element through the at least one signal path; receiving calibration signals based on the transmitted output; and calibrating the at least one configurable analog element based on the received calibration signal and configuration of the at least one signal path.
 38. The method of claim 37, wherein the at least one configurable analog element is an analog-to-digital converter (ADC), the ADC configured by parameters defining the at least one signal path.
 39. The method of claim 37, wherein the calibration signals are generated by a development environment coupled to the at least one configurable analog element and the at least one signal path.
 40. The method of claim 39, wherein the development environment generates the plurality of parameters for the at least one configurable analog element and the at least one signal path. 